1. Field of the Invention
The present invention relates to a technology of forming high and low withstand voltage semiconductor devices by adjusting thickness of a gate oxide film.
2. Description of the Related Art
In a conventional method of manufacturing a semiconductor device, an element isolating insulator film is formed on the surface of a silicon substrate. A gate oxide film 100 nm thick is formed within an element formation region surrounded with the element isolating insulator film. A polycrystalline silicon layer is then formed selectively on the top surface of a gate oxide film as a gate electrode. Subsequently, impurities are ion-implanted from the top surface of the gate oxide film using the gate electrode as a mask. A diffusion layer is then formed as a drain region and a source region. This technology is described for instance in FIGS. 2-3 pp. 4-5 in Japanese Patent Application Publication No. 2004-39681.
In an alternative conventional method of manufacturing a semiconductor device, the technology taking the following steps is known. When forming high and low withstand voltage circuits on one substrate, a sacrificial oxide film about 100 nm thick is first formed on the top surface of the substrate. In a region where the high withstand voltage circuit is to be formed, impurities are ion-implanted at an acceleration voltage of about 150 keV from the top surface of the sacrificial oxide film. A well region is then formed in a region where a PMOS transistor of the high withstand voltage circuit, or the like is to be formed. Subsequently, the sacrificial oxide film is removed, and a first gate oxide film about 13 nm thick is formed on the top surface of the substrate of the region where both the circuits are formed. A well region is then formed in a region where a PMOS transistor of the low withstand voltage circuit, or the like is formed. Furthermore, a second gate oxide film about 8 nm thick is formed on the top surface of the substrate of the region where both the circuits are formed so as to form the PMOS transistors of both the circuits or the like. This technology is described for instance in FIGS. 1, 6-11, pp. 6-9 in Japanese Patent Application Publication No. 2004-104141.
As described above, in the conventional methods of manufacturing a semiconductor device, a gate oxide film 100 nm thick is deposited on a region which is surrounded by an element isolating insulator film formed on surface of the silicon substrate. At the same time, the gate oxide film is also deposited in the above thickness on the top surface of the region where a drain region and a source region to be formed. In a self-alignment manner with respect to a gate electrode formed on the top surface of the gate oxide film, a diffusion layer is formed as the drain and source regions. This manufacturing method determines the thickness of the oxide film on the top surface of the drain and source regions depending on the thickness of the gate oxide film. Accordingly, depending on the thickness, an acceleration voltage is determined for when ion-implanting impurities. As a result, if an acceleration voltage increases at ion-implantation, impurities go through the gate electrode, thereby preventing the separate formation of the drain and source regions. At the same time, in order to prevent impurities from going through the gate electrode, the acceleration voltage has to be equal to or lower than a certain value. In this case, however, there is an upper limit to the thickness of the gate oxide film, with the result that a high withstand voltage MOS transistor requiring a desired withstand voltage characteristic sometimes cannot be formed.
Also in the conventional methods of manufacturing a semiconductor device, a sacrificial oxide film is deposited on the top surface of the substrate of the region where the high withstand voltage circuit and the low withstand voltage circuit are formed. The sacrificial oxide film is used as an oxide film at a time when forming the well region in the region where the high withstand voltage circuit is formed. Then after forming the element isolating insulator film in the high and low withstand voltage circuits, the sacrificial oxide film is removed. Subsequently, a gate oxide film of desired thickness is deposited on each of the regions where the high and low withstand voltage circuits are formed. This manufacturing method requires the sacrificial oxide film to be formed by the time the element isolating insulator film is formed. As a result, its cost becomes higher and manufacturing steps become complicated.